sv-parser - SystemVerilog parser library fully compliant with IEEE 1800-2017 written in Rust

💾 https://github.com/dalance/sv-parser

#parser #lexer #sv #systemverilog #rust
@fpgasic

BENDER - a dependency management tool for hardware design projects written in Rust.

It provides a way to define dependencies among IPs, execute unit tests, and verify that the source files are valid input for various simulation and synthesis tools.

Principles
▫️Be as opt-in as possible
▫️Allow for reproducible builds
▫️Collect source files
▫️Manage dependencies
▫️Generate tool scripts

💾 https://github.com/pulp-platform/bender
📄 https://pulp-platform.org/docs/riscv_workshop_zurich/bender_wosh2019.pdf

#build #buildsystem #makefile #bender #ip #dependencies #scripts #rust
@fpgasic

svinst - tool takes a SystemVerilog file as input and produces as output the module(s) declared in that file, along with the module(s) instantiated in each one of those module declarations (written in Rust).

💾 https://github.com/sgherbst/svinst

#parser #parsing #instantiation #sv #systemverilog #rust
@fpgasic

Verilog and SystemVerilog cheatsheet

#verilog #systemverilog #cheatsheet #digitaldesign
@fpgasic

openFPGALoader - Universal utility for programming FPGAs. Compatible with many boards, cables and FPGA from major manufacturers (Xilinx, Altera/Intel, Lattice, Gowin, Efinix, Anlogic, Cologne Chip). openFPGALoader works on Linux, Windows and macOS.

openFPGALoader just released version 0.9.0 with most notable evolutions:
▫️libgpiod and XVC (XilinxInc Virtual Cable) support
▫️ORBTrace mini (DFU) and tang Primer 20K support
▫️GW2A, new Kintex models, ZynqMP Ultrascale (and Plus)

💾 https://github.com/trabucayre/openFPGALoader/releases/tag/v0.9.0
📄 https://trabucayre.github.io/openFPGALoader/

#jtag #loader #verilog #xvc #dfu #bitstream #ft2232
@fpgasic

Versatile list of HDL lint tools

📄 https://airhdl.com/blog/2017/02/08/fpga-lint-tools/
(updated August 2022)

#lint #linter #sv #verilog #vhdl
@fpgasic

sv2chisel - SystemVerilog to Chisel Translator

💾 Code
📄 Paper
📄 Features & Limitations

#SV #verilog #chisel #translator

@embedoka

Rosetta - Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs

It contains six fully-developed applications from machine learning and image/video processing domains, where each benchmark consists multiple compute kernels that expose diverse sources of parallelism.

These applications are developed under realistic design constraints, and are optimized at both kernel-level and application-level with the advanced features of HLS tools to meet these constraints.

💾 Code
📄 Paper


#hls #fpga #benchmark
@fpgasic

VCD command line viewer for Windows, Linux and MacOS

Features:
▫️Outputs in YAML format
▫️Querying (unix pipe)
▫️Styling
▫️Auto-Refresh


💾 https://github.com/yne/vcd

#vcd #dump #waveform #testbench #waves #documentation
@fpgasic

VeriGen: A Large Language Model for Verilog Code Generation

The next step getting a Verilog fine-tuned LLM to generate the RTL; then we can kick-back & watch the whole SoC emerge autonomously. Upon testing with a more diverse and complex problem set, we find that the fine-tuned model shows competitive performance against state-of-the-art gpt-3.5-turbo, excelling in certain scenarios. Notably, it demonstrates a 41% improvement in generating syntactically correct Verilog code across various problem categories compared to its pre-trained counterpart, highlighting the potential of smaller, in-house LLMs in hardware design automation.

💾 https://arxiv.org/abs/2308.00708

#verilog #sv #codegen #llm
@fpgasic

OpenVAF - an innovative Verilog-A compiler for use in circuit simulator. The major aim of this Project is to provide a high-quality standard compliant compiler for Verilog-A.

Features:
▫️fast compile times (usually below 1 second for most compact models)
▫️high-quality user interface
▫️easy setup
▫️fast simulations surpassing existing solutions by 30%-60%

OpenVAF currently contains the following useable projects:
1️⃣ VerilogAE allows obtaining model equations (calculates the value of a single Variable) from Verilog-A files
2️⃣ Melange is an experimental circuit simulator that leverage OpenVAF to gain access to compact models

Links:
📄 openvaf.semimod.de/
💾 github.com/pascalkuthe/OpenVAF

#simulation #model #veriloga
@fpgasic

Generate Compilers from Hardware Models

Compiler backends should be automatically generated from hardware design language (HDL) models of the hardware they target. Generating compiler components directly from HDL can provide stronger correctness guarantees, ease development effort, and encourage hardware exploration. Past work has already championed this idea; here we argue that advances in program synthesis make the approach more feasible. We present a concrete example by demonstrating how FPGA technology mappers can be automatically generated from SystemVerilog models of an FPGA's primitives using program synthesis.

💾 https://arxiv.org/abs/2305.09580

@vlsihub

Ramulator - a Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies, and various academic proposals.

Ramulator supports a wide array of commercial DRAM standards:
▫️DDR3, DDR4
▫️LPDDR3, LPDDR4
▫️GDDR5
▫️WIO, WIO2
▫️HBM
▫️SALP
▫️TL-DRAM
▫️RowClone
▫️DSARP

Links:
📄 http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
💾 https://github.com/CMU-SAFARI/ramulator

#ram #model #dram #ddr #hbm
@fpgasic

Ramulator v2 - a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques).

Ramulator 2.0 provides the DRAM models for the following standards:
▫️DDR3, DDR4, DDR5
▫️LPDDR5
▫️GDDR6
▫️HBM2, HBM3

Links:
📄 https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
💾 https://github.com/CMU-SAFARI/ramulator2

#ram #model #dram #ddr #hbm
@fpgasic

CompressedLUT - a tool for lossless compression of lookup tables and generation of their hardware files in Verilog and C++ for RTL and HLS designs.

Links:
📄 https://doi.org/10.1145/3626202.3637575
💾 https://github.com/kiabuzz/CompressedLUT

#acceleration #LUT #lookuptable #lossless #compression #table-size-reduction #table-based-function-implementation
@fpgasic