One of my favorite part of UG949: RTL designer should know into which one primitives (and how many logic levels) infers strings of HDL

Open source tool for reading and writing Vivado design checkpoint (DCP) files. Its mission is to enable power users greater flexibility in customizing solutions http://www.rapidwright.io/ #DCP #Vivado

RapidWright: Enabling Custom Crafted Implementations for FPGAs #RapidWright #Vivado #DCP

Yet another solution (IP+driver) for DMA over PCI-E for Linux/Windows Xilinx/Altera. http://xillybus.com/ #DMA #PCI-E #RIFFA #Xillybus

Vivado Workflow for Generating Relocatable, Out-Of-Context End-User Configuration Tiles

https://github.com/bgottschall/reloc
#Xilinx #PR #OOC #tiles #PartialReconfiguration #PBlock #HierarhicalDesign #OutOfContext

Designing Relocatable Partitions with Vivado Design Suite
#Xilinx #PR #OOC #tiles #PartialReconfiguration #PBlock #HierarhicalDesign #OutOfContext #PDF

Useful code snippet for helping Super Logic Region (SLR) crossing in SSI Xilinx devices (based on slr crossing reg slice code):
https://github.com/nslmike/useful_stuff/blob/master/slr_crossing/slr_cross.v

#SLR #Xilinx #PR #verlog #crossing

Following command retrieves
the TEMPERATURE property from connected FPGA:
get_property TEMPERATURE [get_hw_sysmons]
To report all properties of HW_SYSMON use this in TCL console: report_property -all [lindex [get_hw_sysmons] 0]
#SysMon #TCL #XADC #Xilinx #Telemetry

Multi-Pumping approach for Resource Reduction on Xilinx FPGAs

#DSP48 #ResourceSharing #MultiPumping #MPM #Xilinx

Multi-Pumping approach for Resource Reduction on Xilinx FPGAs

#DSP48 #ResourceSharing #MultiPumping #MPM #Xilinx

Useful attributes for DSP sharing in Vivado 2018.3: DSP_FOLDING and DSP_FOLDING_FASTCLOCK

#UG901 #DSP48 #ResourceSharing #MultiPumping #MPM #Xilinx

“Golden ratio” LUT:FF from UltraFast Design Methodology #UG949 #Xilinx

LiteX is a FPGA design/SoC builder that can be used to build cores, create SoCs and full FPGA designs

https://github.com/enjoy-digital/litex

#Migen #MiSoC #LM32 #Mor1kx #PicoRV32 #VexRiscv #SoC #BuildSystem

Bitstream Interpretation Library (BIL) for reading and interpreting bitstream files targeted at Xilinx FPGA:

- Configuration raw data extraction from bitstream files
- XDL design regeneration out of configuration raw data
- Automated configuration mapping analyzation of a device

https://github.com/florianbenz/bil
#Xilinx #bitstream #BIL #XDL #XDLRC #RAW

Optionally run optimization if there are timing violations after placement

if {[ get_property SLACK [ get_timing_paths -max_paths 1 -nworst 1 -setup ] ] < 0 } {
    puts "INFO :: Found setup timing violations. Running physical optimization once."
    phys_opt_design -directive AggressiveExplore
    phys_opt_design -directive AlternateReplication
    phys_opt_design -directive AggressiveFanoutOpt
}

#Xilinx #Vivado #phys_opt_design #TCL #automation #slack #violation

Automation of Vivado installation on Windows using PowerShell

https://gist.github.com/steelcowboy/4897883fb25082248d64b2f64c782d0d

#Xilinx #Vivado #PowerShell #Windows #Automation @fpgasic

A demo to write to BRAM from File and read from BRAM to file for JTAG2AXI IP Core

https://gist.github.com/imrickysu/a30afc117ac7397fdff6

#Xilinx #Vivado #BRAM #JTAG2AXI @fpgasic

To get eFuse DNA Device ID from Xilinx FPGA:
vivado -mode batch -source get_dna.tcl

https://gist.github.com/kylemanna/d177fd0d562f23d419553689252ceab7

#Xilinx #Vivado #DNA #DeviceID @fpgasic

Good example to start using design automation scripts to program bitstream into Xilinx FPGAs on Vivado CLI

https://github.com/lnls-dig/fpga-programming

#Xilinx #Vivado #CLI #TCL #JTAG @fpgasic

SymbiFlow is a work-in-progress FOSS Verilog-to-Bitstream (end-to-end) FPGA synthesis flow, currently targeting Xilinx 7-Series, Lattice iCE40 and Lattice ECP5 FPGAs. Think of it as the GCC of FPGAs.

https://symbiflow.github.io/
https://github.com/SymbiFlow

#xilinx #yosys #ice40 #series7 #latticesemi