Versatile list of HDL lint tools

📄 https://airhdl.com/blog/2017/02/08/fpga-lint-tools/
(updated August 2022)

#lint #linter #sv #verilog #vhdl
@fpgasic

sv2chisel - SystemVerilog to Chisel Translator

💾 Code
📄 Paper
📄 Features & Limitations

#SV #verilog #chisel #translator

@embedoka

Rosetta - Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs

It contains six fully-developed applications from machine learning and image/video processing domains, where each benchmark consists multiple compute kernels that expose diverse sources of parallelism.

These applications are developed under realistic design constraints, and are optimized at both kernel-level and application-level with the advanced features of HLS tools to meet these constraints.

💾 Code
📄 Paper


#hls #fpga #benchmark
@fpgasic

VCD command line viewer for Windows, Linux and MacOS

Features:
▫️Outputs in YAML format
▫️Querying (unix pipe)
▫️Styling
▫️Auto-Refresh


💾 https://github.com/yne/vcd

#vcd #dump #waveform #testbench #waves #documentation
@fpgasic

VeriGen: A Large Language Model for Verilog Code Generation

The next step getting a Verilog fine-tuned LLM to generate the RTL; then we can kick-back & watch the whole SoC emerge autonomously. Upon testing with a more diverse and complex problem set, we find that the fine-tuned model shows competitive performance against state-of-the-art gpt-3.5-turbo, excelling in certain scenarios. Notably, it demonstrates a 41% improvement in generating syntactically correct Verilog code across various problem categories compared to its pre-trained counterpart, highlighting the potential of smaller, in-house LLMs in hardware design automation.

💾 https://arxiv.org/abs/2308.00708

#verilog #sv #codegen #llm
@fpgasic

OpenVAF - an innovative Verilog-A compiler for use in circuit simulator. The major aim of this Project is to provide a high-quality standard compliant compiler for Verilog-A.

Features:
▫️fast compile times (usually below 1 second for most compact models)
▫️high-quality user interface
▫️easy setup
▫️fast simulations surpassing existing solutions by 30%-60%

OpenVAF currently contains the following useable projects:
1️⃣ VerilogAE allows obtaining model equations (calculates the value of a single Variable) from Verilog-A files
2️⃣ Melange is an experimental circuit simulator that leverage OpenVAF to gain access to compact models

Links:
📄 openvaf.semimod.de/
💾 github.com/pascalkuthe/OpenVAF

#simulation #model #veriloga
@fpgasic

Generate Compilers from Hardware Models

Compiler backends should be automatically generated from hardware design language (HDL) models of the hardware they target. Generating compiler components directly from HDL can provide stronger correctness guarantees, ease development effort, and encourage hardware exploration. Past work has already championed this idea; here we argue that advances in program synthesis make the approach more feasible. We present a concrete example by demonstrating how FPGA technology mappers can be automatically generated from SystemVerilog models of an FPGA's primitives using program synthesis.

💾 https://arxiv.org/abs/2305.09580

@vlsihub

Ramulator - a Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies, and various academic proposals.

Ramulator supports a wide array of commercial DRAM standards:
▫️DDR3, DDR4
▫️LPDDR3, LPDDR4
▫️GDDR5
▫️WIO, WIO2
▫️HBM
▫️SALP
▫️TL-DRAM
▫️RowClone
▫️DSARP

Links:
📄 http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
💾 https://github.com/CMU-SAFARI/ramulator

#ram #model #dram #ddr #hbm
@fpgasic

Ramulator v2 - a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques).

Ramulator 2.0 provides the DRAM models for the following standards:
▫️DDR3, DDR4, DDR5
▫️LPDDR5
▫️GDDR6
▫️HBM2, HBM3

Links:
📄 https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
💾 https://github.com/CMU-SAFARI/ramulator2

#ram #model #dram #ddr #hbm
@fpgasic

CompressedLUT - a tool for lossless compression of lookup tables and generation of their hardware files in Verilog and C++ for RTL and HLS designs.

Links:
📄 https://doi.org/10.1145/3626202.3637575
💾 https://github.com/kiabuzz/CompressedLUT

#acceleration #LUT #lookuptable #lossless #compression #table-size-reduction #table-based-function-implementation
@fpgasic

DUTCTL: A Flexible Open-Source Framework for Rapid Bring-Up, Characterization, and Remote Operation of Custom-Silicon RISC-V SoCs

https://pulp-platform.org/docs/riscvmunich2024/RISCV_europe_summit_2024_DUTCTL_poster.pdf

@vlsihub

The new taste is unlocked: BiCMOS

Now IHP providing not only 𝐨𝐩𝐞𝐧-𝐬𝐨𝐮𝐫𝐜𝐞 𝐏𝐃𝐊 but also 𝐟𝐫𝐞𝐞 𝐚𝐜𝐜𝐞𝐬𝐬 𝐭𝐨 𝐌𝐏𝐖 𝐫𝐮𝐧𝐬 to turn your designs into physical chips. This service is available exclusively for non-commercial projects.

💾 https://ihp-open-ip.readthedocs.io/en/latest/

#IHP #PDK #MPW #BICMOS
@fpgasic

Did you know that Xilinx FPGA have Dynamically Reconfigurable Look-Up Table (LUT)?
It's called CFGLUT5

Note: This component occupies one of the eight LUT6 components within a CLBM.

#UG974 #Xilinx #recongif

This element is a runtime, dynamically reconfigurable, LUT5 that enables the changing of the function of the LUT during circuit operation. Using the CDI pin, a
new INIT to change the logical function.

FloorSet: The First Million-Scale Dataset for SoC Design Planning.

FloorSet is aimed at advancing machine learning for floorplanning physical layouts of systems-on-a-chip (SoCs) and its sub-systems. It features 2 million synthetic benchmark circuits that capture real design constraints and objectives, all carefully sampled from actual design distributions.

FloorSet addresses key challenges of training-data availability and reproducibility in the chip-design world, driving fundamental research in large-scale constrained optimization problems.

Links:
📄 https://arxiv.org/abs/2405.05480
💾 https://github.com/IntelLabs/FloorSet

#floorplan #SoC #MLaimed #CAE #opensource
@fpgasic

Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA

In terms of benchmarking memory, it can be done better on FPGA, rather than on CPU/GPU. When benchmarking memory on an FPGA, the benchmarking hardware engine can directly attach to the memory such that there is no noise between the targeted memory and the benchmarking engine.

With Shuhai, before implementing the concrete application that contains a particular memory access pattern on the FPGA, we are able to benchmark the corresponding memory access pattern to make sure that the memory side will not be the bottleneck.

Links:
📄 https://ieeexplore.ieee.org/document/9114755
💾 https://github.com/RC4ML/Shuhai

#memory #ddr #hbm #benchmark
@fpgasic