[WiP] ligeia - replacement for GTKWave, written in Rust with high-performance and larger-than-memory traces in mind.

https://github.com/lachlansneff/ligeia

#rust #VCD #dump #GTKWave
@fpgasic

🛠 IEEE P1735 decryptor for VHDL

This tool allow to recover full source code of encrypted module (provided you have an extracted private key from the software you're using). Usually software vendors do not care much about hiding their private keys. The decryption is done in two stages:

1️⃣ using the private key, a session key is decrypted using RSA decryption procedure
2️⃣ data block is decoded using this session key and AES-128-CBC decryption procedure

💾 https://github.com/dmitrodem/p1735_decryptor

#decryptor #python #IP #VHDL #P1735 #encryption #protection #Aldec
@fpgasic

fp2p - FPGA Port To Pin tool.

Utility for safe and reusable port to pin assignment in multi-board FPGA designs.

The implementation has two main goals, safety (check as many potential human mistakes as possible) and reusability (reuse connections mappings, defined in files, in multiple designs). It is fully declarative and programming language-agnostic from the users perspective.

https://github.com/m-kru/fp2p

#FPGA #pinout #pin #multiboard #python
@fpgasic

Verilog-HDL/SystemVerilog/Bluespec support for VS Code

Features
▫️ Syntax Highlighting
◦ Verilog
◦ SystemVerilog
◦ Bluespec SystemVerilog
◦ Vivado UCF constraints
◦ Synopsys Design Constraints
▫️Simple Snippets
▫️Linting support from:
◦ Icarus Verilog
◦ Vivado Simulation
◦ Modelsim
◦ Verilator
▫️Ctags Integration
◦ Autocomplete
◦ Document Symbols Outline
◦ Hover over variable declaration
◦ Go to Definition & Peek Definition
◦ Module Instantiation

https://github.com/mshr-h/vscode-verilog-hdl-support

#VScode #MS #verilog #SV #bluespec #lint snippets #syntax #icarus #modelsim #verilator
@fpgasic

Dockerize Synopsys/Cadence EDA tools - is the Dockerfiles to dockerize popular EDA tools.

With docker images we could do:

▫️Build/test your design on the cloud server
▫️Maintain tools with as many different version as you want without issues
▫️Provide tools for you or your peer's desktop computer regardless of which kind of Linux you are using
▫️Continuous Integration (CI)

💾 https://github.com/limerainne/Dockerize-EDA

#docker #cadence #synopsys #eda
@fpgasic

OpenRAM - an Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.

💾 https://github.com/VLSIDA/OpenRAM

#ASIC #verilog #python #memory #SRAM #generator #GDS #netlist #netgen #magic #Ngspice
@fpgasic

pysv - a lightweight Python library that allows functional models to be written in Python and then executed inside standard SystemVerilog simulators, via DPI.

Supported Simulators
▫️Cadence Xcelium
▫️Synopsys VCS
▫️Mentor Questa
▫️Vivado Simulator
▫️Verilator


💾 https://github.com/Kuree/pysv

#SV #systemverilog #python #simulation #cosimulation
@fpgasic

PipelineC - a C-like hardware description language (HDL) adding HLS(high level synthesis)-like automatic pipelining as a language construct/compiler feature.

💾 https://github.com/JulianKemmerer/PipelineC

#HLS #C #VHDL #python #pipelines #FPGA
@fpgasic

asciiwave - WaveDrom to ASCII art

💾 https://github.com/Wren6991/asciiwave

#waves #diagram #python #asciiart #wavedrom
@fpgasic

CACTI is an integrated cache and memory access time, cycle time, area, leakage, and dynamic power model. By integrating all these models together, users can have confidence that tradeoffs between time, power, and area are all based on the same assumptions and, hence, are mutually consistent. CACTI is intended for use by computer architects to better understand the performance tradeoffs inherent in memory system organizations.

Power, delay, area, and cycle time model for
▫️ direct mapped caches
▫️ set-associative caches
▫️ fully associative caches
▫️ Embedded DRAM memories
▫️ Commodity DRAM memories

💾 https://github.com/HewlettPackard/cacti
📄 https://hpl.hp.com/research/cacti/


#memory #cache #PPA #estimation
@fpgasic

Scripts for archiving legacy Altera software

n 2020, Intel published Customer Advisories ADV2011 and ADV2030 which formally discontinued MAX+PLUS II entirely and Quartus II versions released prior to 2014. Downloads of these software were removed from Intel's FPGA download center. By researching the various download infrastructures used by Altera over time, some versions were discovered to still be available if you knew where to look. This repository provides scripts and cached versions of metadata used to discover these versions and enable bulk download of them.

💾 https://github.com/kc8apf/altera_archiving

#Altera #FPGA #Quartus #Legacy
@fpgasic

Silice - A language for hardcoding Algorithms into FPGA hardware

It provides a thin abstraction above Verilog (a typical hardware description language), simplifying design without loosing precise control over the hardware. It gives the (optional) ability to write parts of your design as sequences of operations, subroutines that can be called, and to use control flow statements such as while and break. At the same time, Silice lets you fully exploit the parallelism of FPGA architectures, describing operations and algorithms that run in parallel and are precisely in sync.

💾 https://github.com/sylefeb/Silice

#FPGA #HLS #language
@fpgasic

TerosHDL 2.0.0 has been released. You can install it from VSCode market.

Features:
▫️Support for VHDL, Verilog, System Verilog
▫️Windows, Linux, Mac
▫️Simulators and tools support: Vivado, ModelSim, GHDL, Verilator, Icarus, VCS, Yosys, VUnit, cocotb, Diamond, Icestorm, ISE, Quartus, Radiant, Spyglass, Symbiflow, Trellis, Xcelium...
▫️Go to definition
▫️Hover
▫️Hiterachy viewer
▫️Dependencies viewer
▫️Syntax highlighting
▫️Template generator
▫️Automatic documentation
▫️Command line documenter
▫️Verilog/SV schematic viewer
▫️Errors linter
▫️Style linter: Verible
▫️Code formatting
▫️State machine viewer
▫️State machine designer
▫️Code snippets and grammar

💾 https://marketplace.visualstudio.com/items?itemName=teros-technology.teroshdl
📄 https://terostechnology.github.io/terosHDLdoc/

#verilog #vhdl #systemverilog #teroshdl #vunit #edalize #wavedrom #vscode
@fpgasic

Open-Source RISC-V GPGPU Project

Researchers have found a way to enable CUDA software toolkit support on a RISC-V GPGPU project called Vortex. The Vortex RISC-V GPGPU aims to provide a full-system RISC-V GPU based on RV32IMF ISA. That means 32-bit cores that can be scaled from 1-core to 32-core GPU designs. It supports OpenCL 1.2 graphics API, and today it got support for some CUDA action as well.

💾 https://www.tgoop.com/ipcores/91
📄 https://www.tomshardware.com/news/risc-v-runs-cuda

#RISCV #GPGPU #GPU #FPGA #CUDA #Nvidia
@fpgasic

OpenTimer - a High-Performance Timing Analysis Tool for VLSI Systems.

OpenTimer is a new static timing analysis (STA) tool to help IC designers quickly verify the circuit timing. It is developed completely from the ground up using C++17 to efficiently support parallel and incremental timing.

Features:
▫️Industry standard format (.lib, .v, .spef, .sdc) support
▫️Graph- and path-based timing analysis
▫️Parallel incremental timing for fast timing closure
▫️Award-winning tools and golden timers in CAD Contests

💾 https://github.com/OpenTimer/OpenTimer

#vlsi #asic #sta #statictiminganalysis #circuitanalysis
@fpgasic

Logic - CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Features:
▫️Cross platform, cross IDE
▫️No need to create separate scripts for simulation and synthesis
▫️No need to create separate scripts for different tools (Quartus, Vivado, ModelSim, ...)
▫️Supports incremental compilation
▫️Supports parallel compilation
▫️Maintain the same file consistency between simulation and synthesis for different tools
▫️Share the same HDL source code base and IP cores for various FPGA projects
▫️Integration with CI and CD like Jenkins, Hudson, GitLab, etc.
▫️Run RTL unit tests under ctest: pass/fail, time execution, timeout, parallel execution, tests selection
▫️Run the same unit tests with different parameters
▫️Easy to integrate with other projects as git submodule
▫️Custom UVM printers: JSON
▫️Modern HDL testing library written in C++11 using UVM-SystemC
▫️Support for Clang 3.5+
▫️Support for GCC 4.9+

💾 https://github.com/tymonx/logic
📄 https://github.com/tymonx/logic/wiki

#vlsi #asic #build #automation #ci #cd
@fpgasic

Vivado 2021.2 is available now

💾 Download (be careful! 72GB 😱)
📄 What's New Vivado
📄 What's New Vitis

#Xilinx #Vivado #Vitis #HLS
@fpgasic

Have you ever wondered how to explain the difference between FPGA and CPU?

CPU vs FPGA

@fpgasic

svlint - awesome SystemVerilog linter written in Rust

💾 https://github.com/dalance/svlint
📄 https://github.com/dpretet/dotfiles/blob/master/svlint.toml

#lint #linter #sv #systemverilog #rust
@fpgasic

SVUnit - an open-source test framework for ASIC and FPGA developers writing Verilog and SystemVerilog code.

SVUnit is automated, fast, lightweight and easy to use making it the only SystemVerilog test framework in existence suited to both design and verification engineers that aspire to high quality code and low bug rates.

💾 https://github.com/svunit/svunit
📄 http://www.agilesoc.com/svunit

#test #testbench #verification #sv #systemverilog #svunit
@fpgasic