А што если кто-то сделает UVM окружение для тестирования функциональности аппаратных ресурсов в ПЛИС. Так вот, какой то дядя это сделал
https://github.com/Mekky7/UVM-enviroment-of-Spartan-6-FPGA-DSP48A1-
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Ориджинал пост фром линкедин
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https://github.com/Mekky7/UVM-enviroment-of-Spartan-6-FPGA-DSP48A1-
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Ориджинал пост фром линкедин
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Hey all, I want to share with you my latest project in digital verification field, I have managed to implement UVM testing environment of Spartan-6 FPGA DSP48A1 architecture from Xilinx I have tested the full configurations, achieving 99.61 % code coverage in the parameterised design and i have made equivalent models for both the sequential and combinational configuration in my scoreboard, It was such a great project to enhance my knowledge in UVM and Verification of pipelined architectures.
you will get the project files in my GitHub link: https://lnkd.in/duDsr_WY
all you will do is to run the do file attached to see the figures attached below.
If you have any questions don't hesitate to ask me and I will be very happy to answer and help you.
tgoop.com/fpgasystems_events/2820
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А што если кто-то сделает UVM окружение для тестирования функциональности аппаратных ресурсов в ПЛИС. Так вот, какой то дядя это сделал
https://github.com/Mekky7/UVM-enviroment-of-Spartan-6-FPGA-DSP48A1-
===
Ориджинал пост фром линкедин
===
https://github.com/Mekky7/UVM-enviroment-of-Spartan-6-FPGA-DSP48A1-
===
Ориджинал пост фром линкедин
===
Hey all, I want to share with you my latest project in digital verification field, I have managed to implement UVM testing environment of Spartan-6 FPGA DSP48A1 architecture from Xilinx I have tested the full configurations, achieving 99.61 % code coverage in the parameterised design and i have made equivalent models for both the sequential and combinational configuration in my scoreboard, It was such a great project to enhance my knowledge in UVM and Verification of pipelined architectures.
you will get the project files in my GitHub link: https://lnkd.in/duDsr_WY
all you will do is to run the do file attached to see the figures attached below.
If you have any questions don't hesitate to ask me and I will be very happy to answer and help you.
BY FPGA-Systems Events
Share with your friend now:
tgoop.com/fpgasystems_events/2820