VLSI HUB

Generate Compilers from Hardware Models

Compiler backends should be automatically generated from hardware design language (HDL) models of the hardware they target. Generating compiler components directly from HDL can provide stronger correctness guarantees, ease development effort, and encourage hardware exploration. Past work has already championed this idea; here we argue that advances in program synthesis make the approach more feasible. We present a concrete example by demonstrating how FPGA technology mappers can be automatically generated from SystemVerilog models of an FPGA's primitives using program synthesis.

💾 https://arxiv.org/abs/2305.09580

@vlsihub

www.tgoop.com/vlsihub/405

4.6K viewsDmitry Murzinov, Aug 30, 2023 at 15:19

Generate Compilers from Hardware Models

Compiler backends should be automatically generated from hardware design language (HDL) models of the hardware they target. Generating compiler components directly from HDL can provide stronger correctness guarantees, ease development effort, and encourage hardware exploration. Past work has already championed this idea; here we argue that advances in program synthesis make the approach more feasible. We present a concrete example by demonstrating how FPGA technology mappers can be automatically generated from SystemVerilog models of an FPGA's primitives using program synthesis.

💾 https://arxiv.org/abs/2305.09580

@vlsihub

BY VLSI HUB